The present invention relates to a mismatch detection method in trace identifiers contained in data frames, in particular SDH (Synchronous Digital Hierarchy) coded data frames within a telecommunication network, wherein said received trace identifiers are compared with expected trace identifiers in determined locations of the communication network, to detect if a misconnection event has occurred and generate an alarm signal.
During the past recent years SDH protocol has been increasingly adopted in the field of telecommunication networks.
A technique has been developed under SDH protocol to detect the so-called misconnections. The latter occur whenever information is inserted in a given input or transmitter in the network and a certain type of connection has to be provided within the network, in order to let said information reach a given output or receiver. A misconnection occurs when information is received at a network output from a wrong or undue input, e.g. due to a wrong routing of said information.
Therefore, a Trace Identifier has been developed and standardized to detect misconnections. Said trace identifier consists of a 1-byte or 16-bytes string, as the case may be, which is introduced in the telecommunication network. The receiver reached by the string has to validate the received string to make sure it is a valid string, not corrupted by line errors, and compare it with an expected value, to verify that it is connected with the right transmitter. If this condition is not satisfied, the receiver has to issue a trace identifier mismatch signal (TIM).
A trace identifier is specified by many standarization protocols, such as ITU-T G707 and ITU-T G783. The trace identifier for the 1-byte string has a simple code whose values range from 0 to 255; in the 16-bytes string or frame the first byte has a frame start marker bit and it also includes in 7 bits the result of a Cyclic Redundancy Code (CRC-7) calculation carried out on the previous transmitted frame. The above standards provide insertion of the calculation result of Cyclic Redundancy Code for error detection, i.e. the function of an error correction code. The cyclic redundancy code algorithm will be described more in detail later, specifically with reference to FIG. 3. The remaining 15 bytes contain 15 characters each, the same in each frame. FIG. 1 shows general schematics of the trace identifier TI as defined by the above standards. A 16-bytes trace identifier TI-16 consists of 16-bytes, BY1 to BY16, each one consisting of 8 bits, B1 to B8. Each first bit B1 of each byte BY1 . . . BY16 represents the frame start marker MK. Bits B2 . . . B8 of the first byte BY1 are C1 . . . C7 bits forming a validation word WCRC7, and they are the result of the cyclic redundancy code operation over the previous transmitted trace identifier TI. The remaining bits, indicated as a whole with X, form the data bits Di of the trace identifier TI, which belong to each input wherefrom the frame is coming. A 1-byte trace identifier TI-1 merely consists of 1-byte BY1, which is formed by 8 bits B1 to B8 representing a number ranging 0 to 255.
However, the above standards do not concern any methods to handle this trace identifier in order to issue an alarm signal in a misconnection event.
EP 0 766 421 (D1), which is considered the closest prior art, discloses a mismatch detection method in trace identifiers contained in SDH-coded data frames. D1 provides for two check steps, a validation step and a comparison step between the received trace identifier and an expected trace identifier. The two steps in D1 are not carried out in parallel and furthermore are executed only using 16 bytes trace identifiers and through the so called persistency check method. Persistency check with depth N means that a trace identifier which is periodically transmitted has to be observed at the receiving side for N consecutive times to be considered valid (i.e. not affected by transmission errors). This results in an apparatus requiring an high number (48) of memory cells for storing three 16-bytes strings and operating in a slow manner. Furthermore, the method and apparatus according to D1 is not usable for 1-byte string trace identifiers.
Moreover, no other valid mismatch detection methods are available in trace identifiers, in particular any methods able to produce TIM signals, considering both the probability of line error events and standard requirements in respect of misconnection detection speed.
It is the main object of the present invention to overcome the above drawbacks and provide a mismatch detection method and circuit in trace identifiers able to efficiently detect misconnections events, which is compatible with the standards and considering both the probability of transmission line error and misconnection detection speed. The method and circuit according to the invention should use a reduced amount of memory to process trace identifiers, both 1-byte and 16-bytes trace identifiers.
According to the present invention, a mismatch detection method and circuit is provided incorporating the features of the annexed claims, which form an integral part of the present description.
The mismatch detection method according to the invention comprises the steps of: a) validating the received trace identifier and issuing a correspondent validation signal; b) comparing the received trace identifier with an expected trace identifier and issuing a correspondent match signal; c) evaluating the validation signal and the match signal; and d) generating a matching state signal according to the result of the evaluation as per step c), and is characterized in that the steps a) and b) are executed in parallel and further in that steps a) to d) are provided both for 16-bytes length trace identifiers and 1-byte length trace identifiers, wherein the validating step is carried out through a Cyclic Redundancy Code check in case of 16-bytes length trace identifiers and a Persistency Check in case of 1-byte length trace identifiers.
The mismatch detection circuit according to the invention comprises: means for validating the received trace identifiers and issuing a correspondent validation signal; means for comparing the received trace identifier with an expected trace identifier and issuing a correspondent match signal; means for evaluating the validation signal and the match signal; and means, respondent to said evaluating means, for generating a matching state signal, and is characterized in that said validation means and said match detection means are arranged in parallel with respect to the input of the received trace identifier with both their outputs being connected with a logic means suitable to generate match state signals and in that the circuit is able to operate on both 16-bytes length trace identifiers and 1-byte length trace identifiers, wherein the validating means operate through a Cyclic Redundancy Code check in case of 16-bytes length trace identifiers and a Persistency Check in case of 1-byte length trace identifiers.